The Iax Architecture Interval Arithmetic Extension
نویسندگان
چکیده
In this paper we discuss a processor architecture for interval arithmetic. Firstly it is shown that double precision FPUs can cheaply be split to support single precision interval addition/subtraction or multiplication, secondly we propose hardware support for double precision interval arithmetic and compare the e ort and performance with software implementations on current architectures.
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تاریخ انتشار 1999